Intel architecture specific code such as multiprocessor, virtual memory and exception/interrupt handling. More...

Namespaces
	Arch

Data Structures
class	IntelACPI
	Intel Advanced Configuration and Power Interface (ACPI). More...

class	IntelAPIC
	Intel Advanced Programmable Interrupt Controller (APIC) More...

struct	AoutSymbolTable
	The symbol table for a.out. More...

struct	ElfSectionHeaderTable
	The section header table for ELF. More...

struct	MultibootInfo
	The Multiboot information. More...

struct	MultibootModule
	The module class. More...

struct	MultibootMemoryMap
	The MultiBoot memory map. More...

class	IntelCache
	Intel cache management implementation. More...

struct	TSS
	Intel's Task State Segment. More...

struct	Segment
	Segment descriptor used in the GDT. More...

struct	SegRegs
	Segmentation registers. More...

struct	CPURegs
	Structure represents the pusha/popa format. More...

struct	IRQRegs0
	Privileged Interrupt Registers (ring 0) More...

struct	IRQRegs3
	Unprivileged Interrupt Registers (ring 3) More...

struct	CPUState
	Contains all the CPU registers. More...

class	IntelCore
	Intel CPU Core. More...

class	IntelIO
	Intel I/O functions. More...

class	IntelMap
	Defines memory map for Intel systems. More...

class	IntelMP
	Intel Multi-Processor Specification. More...

class	IntelPageDirectory
	Intel page directory implementation. More...

class	IntelPageTable
	Intel second level page table implementation. More...

class	IntelPaging
	Intel virtual memory implementation. More...

class	IntelPIC
	Intel 8259 Programmable Interrupt Controller (PIC). More...

class	IntelPIT
	Intel 8254 Programmable Interrupt Timer (PIT). More...

Macros
#define	MULTIBOOT_HEADER_MAGIC 0x1BADB002
	The magic number for the Multiboot header. More...

#define	MULTIBOOT_HEADER_FLAGS 0x00000003
	The flags for the Multiboot header. More...

#define	MULTIBOOT_HEADER_SIZE 52
	Size of the multiboot header structure. More...

#define	MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
	The magic number passed by a Multiboot-compliant boot loader. More...

#define	cpu_reboot()
	Reboot the system (by sending the a reset signal on the keyboard I/O port) More...

#define	cpu_shutdown()
	Shutdown the machine via ACPI. More...

#define	idle() asm volatile ("hlt");
	Puts the CPU in a lower power consuming state. More...

#define	ltr(sel)
	Loads the Task State Register (LTR) with the given segment. More...

#define	tlb_flush(addr) asm volatile("invlpg (%0)" ::"r" (addr) : "memory")
	Flushes the Translation Lookaside Buffers (TLB) for a single page. More...

#define	tlb_flush_all()
	Flushes all Translation Lookaside Buffers (TLB). More...

#define	MPINFOADDR 0x10000
	Physical memory address for the CoreInfo structure. More...

Typedefs
typedef struct AoutSymbolTable	AoutSymbolTable
	The symbol table for a.out. More...

typedef struct ElfSectionHeaderTable	ElfSectionHeaderTable
	The section header table for ELF. More...

typedef struct MultibootInfo	MultibootInfo
	The Multiboot information. More...

typedef struct MultibootModule	MultibootModule
	The module class. More...

typedef struct MultibootMemoryMap	MultibootMemoryMap
	The MultiBoot memory map. More...

typedef struct TSS	TSS
	Intel's Task State Segment. More...

typedef struct Segment	Segment
	Segment descriptor used in the GDT. More...

typedef struct SegRegs	SegRegs
	Segmentation registers. More...

typedef struct CPURegs	CPURegs
	Structure represents the pusha/popa format. More...

typedef struct IRQRegs0	IRQRegs0
	Privileged Interrupt Registers (ring 0) More...

typedef struct IRQRegs3	IRQRegs3
	Unprivileged Interrupt Registers (ring 3) More...

typedef struct CPUState	CPUState
	Contains all the CPU registers. More...

Functions
C void	bootEntry16 ()
	Entry point in 16-bit real mode. More...

C void	bootEntry32 ()
	Entry point in 32-bit protected mode. More...

C void	multibootEntry ()
	Entry point from GRUB multiboot. More...

C void	multibootToCoreInfo (MultibootInfo *info)
	Convert multiboot info to a CoreInfo struct. More...

u64	timestamp ()
	Reads the CPU's timestamp counter. More...

C void	switchCoreState (Address *currentStack, Address stack)
	Switch Core Stack. More...

C void	loadCoreState ()
	Load Core State. More...

C void	interruptHandler ()
	Interrupt Service Router (ISR) handler. More...

Variables
MultibootInfo	multibootInfo
	Fill in by the early boot process. More...

Segment	gdt []
	Global Descriptor Table. More...

TSS	kernelTss
	Task State Segment. More...

Address	kernelPageDir []
	Kernel page directory. More...

C void(*	interruptRun )(CPUState state)
	Process an interrupt. More...

#define	CR0_PE 0x00000001
	Intel CPU Constants. More...

#define	CR0_PG 0x80000000
	Paged Mode. More...

#define	CR4_TSD 0x00000004
	Timestamp Counter Disable. More...

#define	CR4_PSE (1 << 4)

#define	KERNEL_CS 1
	Kernel Code Segment. More...

#define	KERNEL_CS_SEL 0x8

#define	KERNEL_DS 2
	System Data Segment. More...

#define	KERNEL_DS_SEL 0x10

#define	USER_CS 3
	User Code Segment. More...

#define	USER_CS_SEL (0x18 \| 3)

#define	USER_DS 4
	User Data Segment. More...

#define	USER_DS_SEL (0x20 \| 3)

#define	KERNEL_TSS 5
	Kernel Task State Segment. More...

#define	KERNEL_TSS_SEL 0x28

#define	PAGESHIFT 12
	Intel Memory Constants. More...

#define	DIRSHIFT 22
	Page table bit shift. More...

#define	PAGESIZE 4096
	Intel uses 4K pages. More...

#define	PAGEDIR_MAX 1024
	Number of entries in the page directory. More...

#define	PAGETAB_MAX 1024
	Number of entries in a page table. More...

#define	PAGEMASK 0xfffff000
	Mask to find the page. More...

#define	SECTIONMASK 0xffc00000
	Mask for large 4MiB mappings. More...

#define	MEMALIGN 4
	Memory address alignment. More...

Intel CPU Exceptions
#define	INTEL_DIVZERO 0

#define	INTEL_DEBUGEX 1

#define	INTEL_NMI 2

#define	INTEL_BREAKP 3

#define	INTEL_OVERFLOW 4

#define	INTEL_BOUNDS 5

#define	INTEL_OPCODE 6

#define	INTEL_DEVERR 7

#define	INTEL_DOUBLEF 8

#define	INTEL_COSEG 9

#define	INTEL_TSSERR 10

#define	INTEL_SEGERR 11

#define	INTEL_STACKERR 12

#define	INTEL_GENERR 13

#define	INTEL_PAGEFAULT 14

#define	INTEL_FLOATERR 16

#define	INTEL_ALIGNERR 17

#define	INTEL_MACHCHK 18

#define	INTEL_SIMD 19

#define	INTEL_VIRTERR 20

Intel EFLAGS Register
#define	INTEL_EFLAGS_DEFAULT (1 << 1)

#define	INTEL_EFLAGS_IRQ (1 << 9)

Intel Kernel Traps
Intel specific software interrupts. These functions are called by the user program to invoke the kernel APIs, also known as system calls.
ulong	trapKernel1 (ulong num, ulong arg1)
	Perform a kernel trap with 1 argument. More...

ulong	trapKernel2 (ulong num, ulong arg1, ulong arg2)
	Perform a kernel trap with 2 arguments. More...

ulong	trapKernel3 (ulong num, ulong arg1, ulong arg2, ulong arg3)
	Perform a kernel trap with 3 arguments. More...

ulong	trapKernel4 (ulong num, ulong arg1, ulong arg2, ulong arg3, ulong arg4)
	Perform a kernel trap with 4 arguments. More...

ulong	trapKernel5 (ulong num, ulong arg1, ulong arg2, ulong arg3, ulong arg4, ulong arg5)
	Perform a kernel trap with 5 arguments. More...

Detailed Description

Intel architecture specific code such as multiprocessor, virtual memory and exception/interrupt handling.

Macro Definition Documentation

◆ cpu_reboot

#define cpu_reboot ( )

Value:

({ \
    IntelIO io; \
    io.outb(0x64, 0xfe); \
})

Reboot the system (by sending the a reset signal on the keyboard I/O port)

Definition at line 51 of file IntelCore.h.

◆ cpu_shutdown

#define cpu_shutdown ( )

Value:

({ \
    IntelIO io; \
    io.outw(0xB004, 0x0 | 0x2000); \
})

Shutdown the machine via ACPI.

Todo:: FreeNOS does not yet have a full ACPI implementation. Shutdown now has a bit naive implementation.

See also: http://forum.osdev.org/viewtopic.php?t=16990

Definition at line 64 of file IntelCore.h.

◆ CR0_PE

#define CR0_PE 0x00000001

Intel CPU Constants.

Protected Mode.

Definition at line 38 of file IntelConstant.h.

◆ CR0_PG

#define CR0_PG 0x80000000

Paged Mode.

Definition at line 41 of file IntelConstant.h.

◆ CR4_PSE

#define CR4_PSE (1 << 4)

Definition at line 45 of file IntelConstant.h.

◆ CR4_TSD

#define CR4_TSD 0x00000004

Timestamp Counter Disable.

Definition at line 44 of file IntelConstant.h.

◆ DIRSHIFT

#define DIRSHIFT 22

Page table bit shift.

Definition at line 80 of file IntelConstant.h.

◆ idle

#define idle ( ) asm volatile ("hlt");

Puts the CPU in a lower power consuming state.

Definition at line 73 of file IntelCore.h.

◆ INTEL_ALIGNERR

#define INTEL_ALIGNERR 17

Definition at line 123 of file IntelCore.h.

◆ INTEL_BOUNDS

#define INTEL_BOUNDS 5

Definition at line 112 of file IntelCore.h.

◆ INTEL_BREAKP

#define INTEL_BREAKP 3

Definition at line 110 of file IntelCore.h.

◆ INTEL_COSEG

#define INTEL_COSEG 9

Definition at line 116 of file IntelCore.h.

◆ INTEL_DEBUGEX

#define INTEL_DEBUGEX 1

Definition at line 108 of file IntelCore.h.

◆ INTEL_DEVERR

#define INTEL_DEVERR 7

Definition at line 114 of file IntelCore.h.

◆ INTEL_DIVZERO

#define INTEL_DIVZERO 0

Definition at line 107 of file IntelCore.h.

◆ INTEL_DOUBLEF

#define INTEL_DOUBLEF 8

Definition at line 115 of file IntelCore.h.

◆ INTEL_EFLAGS_DEFAULT

#define INTEL_EFLAGS_DEFAULT (1 << 1)

Definition at line 137 of file IntelCore.h.

◆ INTEL_EFLAGS_IRQ

#define INTEL_EFLAGS_IRQ (1 << 9)

Definition at line 138 of file IntelCore.h.

◆ INTEL_FLOATERR

#define INTEL_FLOATERR 16

Definition at line 122 of file IntelCore.h.

◆ INTEL_GENERR

#define INTEL_GENERR 13

Definition at line 120 of file IntelCore.h.

◆ INTEL_MACHCHK

#define INTEL_MACHCHK 18

Definition at line 124 of file IntelCore.h.

◆ INTEL_NMI

#define INTEL_NMI 2

Definition at line 109 of file IntelCore.h.

◆ INTEL_OPCODE

#define INTEL_OPCODE 6

Definition at line 113 of file IntelCore.h.

◆ INTEL_OVERFLOW

#define INTEL_OVERFLOW 4

Definition at line 111 of file IntelCore.h.

◆ INTEL_PAGEFAULT

#define INTEL_PAGEFAULT 14

Definition at line 121 of file IntelCore.h.

◆ INTEL_SEGERR

#define INTEL_SEGERR 11

Definition at line 118 of file IntelCore.h.

◆ INTEL_SIMD

#define INTEL_SIMD 19

Definition at line 125 of file IntelCore.h.

◆ INTEL_STACKERR

#define INTEL_STACKERR 12

Definition at line 119 of file IntelCore.h.

◆ INTEL_TSSERR

#define INTEL_TSSERR 10

Definition at line 117 of file IntelCore.h.

◆ INTEL_VIRTERR

#define INTEL_VIRTERR 20

Definition at line 126 of file IntelCore.h.

◆ KERNEL_CS

#define KERNEL_CS 1

Kernel Code Segment.

Definition at line 48 of file IntelConstant.h.

◆ KERNEL_CS_SEL

#define KERNEL_CS_SEL 0x8

Definition at line 49 of file IntelConstant.h.

◆ KERNEL_DS

#define KERNEL_DS 2

System Data Segment.

Definition at line 52 of file IntelConstant.h.

◆ KERNEL_DS_SEL

#define KERNEL_DS_SEL 0x10

Definition at line 53 of file IntelConstant.h.

◆ KERNEL_TSS

#define KERNEL_TSS 5

Kernel Task State Segment.

Definition at line 64 of file IntelConstant.h.

◆ KERNEL_TSS_SEL

#define KERNEL_TSS_SEL 0x28

Definition at line 65 of file IntelConstant.h.

◆ ltr

#define ltr ( sel )

Value:

({ \
    u16 tr = sel; \
    asm volatile ("ltr %0\n" :: "r"(tr)); \
})

Loads the Task State Register (LTR) with the given segment.

Parameters

sel	TSS segment selector.

Definition at line 81 of file IntelCore.h.

◆ MEMALIGN

#define MEMALIGN 4

Memory address alignment.

Definition at line 98 of file IntelConstant.h.

◆ MPINFOADDR

#define MPINFOADDR 0x10000

Physical memory address for the CoreInfo structure.

Definition at line 33 of file IntelMP.h.

◆ MULTIBOOT_BOOTLOADER_MAGIC

#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002

The magic number passed by a Multiboot-compliant boot loader.

Definition at line 42 of file IntelBoot.h.

◆ MULTIBOOT_HEADER_FLAGS

#define MULTIBOOT_HEADER_FLAGS 0x00000003

The flags for the Multiboot header.

Definition at line 36 of file IntelBoot.h.

◆ MULTIBOOT_HEADER_MAGIC

#define MULTIBOOT_HEADER_MAGIC 0x1BADB002

The magic number for the Multiboot header.

Definition at line 33 of file IntelBoot.h.

◆ MULTIBOOT_HEADER_SIZE

#define MULTIBOOT_HEADER_SIZE 52

Size of the multiboot header structure.

Definition at line 39 of file IntelBoot.h.

◆ PAGEDIR_MAX

#define PAGEDIR_MAX 1024

Number of entries in the page directory.

Definition at line 86 of file IntelConstant.h.

◆ PAGEMASK

#define PAGEMASK 0xfffff000

Mask to find the page.

Definition at line 92 of file IntelConstant.h.

◆ PAGESHIFT

#define PAGESHIFT 12

Intel Memory Constants.

Page entry bit shift.

Definition at line 77 of file IntelConstant.h.

◆ PAGESIZE

#define PAGESIZE 4096

Intel uses 4K pages.

Definition at line 83 of file IntelConstant.h.

◆ PAGETAB_MAX

#define PAGETAB_MAX 1024

Number of entries in a page table.

Definition at line 89 of file IntelConstant.h.

◆ SECTIONMASK

#define SECTIONMASK 0xffc00000

Mask for large 4MiB mappings.

Definition at line 95 of file IntelConstant.h.

◆ tlb_flush

#define tlb_flush ( addr ) asm volatile("invlpg (%0)" ::"r" (addr) : "memory")

Flushes the Translation Lookaside Buffers (TLB) for a single page.

Parameters

addr	Memory address to flush.

Definition at line 92 of file IntelCore.h.

◆ tlb_flush_all

#define tlb_flush_all ( )

Value:

asm volatile("mov %cr3, %eax\n" \

"mov %eax, %cr3\n")

Flushes all Translation Lookaside Buffers (TLB).

Definition at line 98 of file IntelCore.h.

◆ USER_CS

#define USER_CS 3

User Code Segment.

Definition at line 56 of file IntelConstant.h.

◆ USER_CS_SEL

#define USER_CS_SEL (0x18 | 3)

Definition at line 57 of file IntelConstant.h.

◆ USER_DS

#define USER_DS 4

User Data Segment.

Definition at line 60 of file IntelConstant.h.

◆ USER_DS_SEL

#define USER_DS_SEL (0x20 | 3)

Definition at line 61 of file IntelConstant.h.

Typedef Documentation

◆ AoutSymbolTable

typedef struct AoutSymbolTable AoutSymbolTable

The symbol table for a.out.

◆ CPURegs

typedef struct CPURegs CPURegs

Structure represents the pusha/popa format.

◆ CPUState

typedef struct CPUState CPUState

Contains all the CPU registers.

◆ ElfSectionHeaderTable

typedef struct ElfSectionHeaderTable ElfSectionHeaderTable

The section header table for ELF.

◆ IRQRegs0

typedef struct IRQRegs0 IRQRegs0

Privileged Interrupt Registers (ring 0)

Consumed by a 'iretd'. Does not switch privilege level, i.e. no ESP/SS for ring3 needed.

◆ IRQRegs3

typedef struct IRQRegs3 IRQRegs3

Unprivileged Interrupt Registers (ring 3)

Consumed by a 'iretd'. Changes the privilege level to ring 3, by popping ESP/SS for ring3.

Note that the stack pointer and stack segment are needed in the privilege switch 'iretd', because the stack contains the information needed for a atomic privilege level switch.

◆ MultibootInfo

typedef struct MultibootInfo MultibootInfo

The Multiboot information.

◆ MultibootMemoryMap

typedef struct MultibootMemoryMap MultibootMemoryMap

The MultiBoot memory map.

Note: Be careful that the offset 0 is base_addr_low but no size.

◆ MultibootModule

typedef struct MultibootModule MultibootModule

The module class.

◆ Segment

typedef struct Segment Segment

Segment descriptor used in the GDT.

◆ SegRegs

typedef struct SegRegs SegRegs

Segmentation registers.

◆ TSS

typedef struct TSS TSS

Intel's Task State Segment.

The TSS is mainly used for hardware context switching, which the current implementation does not use. The only fields used are the esp0 and ss0, which contain the kernel stack address and segment used when processing an interrupt.

Function Documentation

◆ bootEntry16()

C void bootEntry16 ( )

Entry point in 16-bit real mode.

Referenced by IntelMP::boot().

◆ bootEntry32()

C void bootEntry32 ( )

Entry point in 32-bit protected mode.

◆ interruptHandler()

C void interruptHandler ( )

Interrupt Service Router (ISR) handler.

This function saves and restores the complete user state on the kernel stack (found via the TSS). After the kernel has finished executing it will restore the user state completely.

◆ loadCoreState()

C void loadCoreState ( )

Load Core State.

This function is used to restore the full state of the Core. It is used by the kernel as a function to initialize the Process register state when it starts the first time.

Referenced by IntelProcess::reset().

◆ multibootEntry()

C void multibootEntry ( )

Entry point from GRUB multiboot.

The Bootstrap Processor (BSP) starts from GRUB. This routine transforms the GRUB multiboot info to a CoreInfo and then continues with bootEntry32.

See also: bootEntry32

◆ multibootToCoreInfo()

C void multibootToCoreInfo ( MultibootInfo * info )

Convert multiboot info to a CoreInfo struct.

Definition at line 25 of file IntelBoot.cpp.

References __end, __start, CoreInfo::bootImageAddress, CoreInfo::bootImageSize, MultibootInfo::cmdline, MemoryBlock::copy(), CoreInfo::coreId, coreInfo, CoreInfo::kernel, KERNEL_PATHLEN, CoreInfo::kernelCommand, MegaByte, CoreInfo::memory, MultibootInfo::memUpper, MultibootModule::modEnd, MultibootInfo::modsAddress, MultibootInfo::modsCount, MultibootModule::modStart, Memory::Range::phys, MemoryBlock::set(), Memory::Range::size, and MultibootModule::string.

◆ switchCoreState()

C void switchCoreState	(	Address *	currentStack,
		Address	stack
	)

Switch Core Stack.

This function only needs to save the current Kernel state, and restore the new Kernel state. It will be used by the kernel to preserve its call stack and registers when it wants to switch to a different Process.

Parameters

currentStack	Address to a pointer to save the current Core state, or ZERO to skip.
stack	Address of the stack to set.

Referenced by IntelProcess::execute().

◆ timestamp()

u64 timestamp ( )

inline

Reads the CPU's timestamp counter.

Returns: 64-bit integer.

Definition at line 41 of file IntelCore.h.

Referenced by BenchMark::exec(), TestData< T >::seed(), and timeString().

◆ trapKernel1()

ulong trapKernel1	(	ulong	num,
		ulong	arg1
	)

inline

Perform a kernel trap with 1 argument.

Parameters

num	Unique number of the handler to execute.
arg1	First argument becomes ECX.

Returns: An integer.

Definition at line 52 of file IntelTraps.h.

◆ trapKernel2()

ulong trapKernel2	(	ulong	num,
		ulong	arg1,
		ulong	arg2
	)

inline

Perform a kernel trap with 2 arguments.

Parameters

num	Unique number of the handler to execute.
arg1	First argument becomes ECX.
arg2	Second argument becomes EBX.

Returns: An integer.

Definition at line 68 of file IntelTraps.h.

◆ trapKernel3()

ulong trapKernel3	(	ulong	num,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3
	)

inline

Perform a kernel trap with 3 arguments.

Parameters

num	Unique number of the handler to execute.
arg1	First argument becomes ECX.
arg2	Second argument becomes EBX.
arg3	Third argument becomes EDX.

Returns: An integer.

Definition at line 85 of file IntelTraps.h.

◆ trapKernel4()

ulong trapKernel4	(	ulong	num,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3,
		ulong	arg4
	)

inline

Perform a kernel trap with 4 arguments.

Parameters

num	Unique number of the handler to execute.
arg1	First argument becomes ECX.
arg2	Second argument becomes EBX.
arg3	Third argument becomes EDX.
arg4	Fourth argument becomes ESI.

Returns: An integer.

Definition at line 104 of file IntelTraps.h.

◆ trapKernel5()

ulong trapKernel5	(	ulong	num,
		ulong	arg1,
		ulong	arg2,
		ulong	arg3,
		ulong	arg4,
		ulong	arg5
	)

inline

Perform a kernel trap with 5 arguments.

Parameters

num	Unique number of the handler to execute.
arg1	First argument becomes ECX.
arg2	Second argument becomes EBX.
arg3	Third argument becomes EDX.
arg4	Fourth argument becomes ESI.
arg5	Fifth argument becomes EDI.

Returns: An integer.

Definition at line 125 of file IntelTraps.h.

Variable Documentation

◆ gdt

Segment gdt[]

Global Descriptor Table.

Referenced by IntelKernel::IntelKernel().

◆ interruptRun

C void(* interruptRun) (CPUState state)

Process an interrupt.

Callback function which is called by interruptHandler() to process an interrupt.

See also: interruptHandler

Referenced by IntelKernel::IntelKernel().

◆ kernelPageDir

Address kernelPageDir[]

Kernel page directory.

◆ kernelTss

TSS kernelTss

Task State Segment.

Referenced by IntelProcess::execute(), and IntelKernel::IntelKernel().

◆ multibootInfo

MultibootInfo multibootInfo

Fill in by the early boot process.

Namespaces

Data Structures

Macros

Typedefs

Functions

Variables

Intel CPU Exceptions

Intel EFLAGS Register

Intel Kernel Traps

Detailed Description

Macro Definition Documentation

◆ cpu_reboot

◆ cpu_shutdown

◆ CR0_PE

◆ CR0_PG

◆ CR4_PSE

◆ CR4_TSD

◆ DIRSHIFT

◆ idle

◆ INTEL_ALIGNERR

◆ INTEL_BOUNDS

◆ INTEL_BREAKP

◆ INTEL_COSEG

◆ INTEL_DEBUGEX

◆ INTEL_DEVERR

◆ INTEL_DIVZERO

◆ INTEL_DOUBLEF

◆ INTEL_EFLAGS_DEFAULT

◆ INTEL_EFLAGS_IRQ

◆ INTEL_FLOATERR

◆ INTEL_GENERR

◆ INTEL_MACHCHK

◆ INTEL_NMI

◆ INTEL_OPCODE

◆ INTEL_OVERFLOW

◆ INTEL_PAGEFAULT

◆ INTEL_SEGERR

◆ INTEL_SIMD

◆ INTEL_STACKERR

◆ INTEL_TSSERR

◆ INTEL_VIRTERR

◆ KERNEL_CS

◆ KERNEL_CS_SEL

◆ KERNEL_DS

◆ KERNEL_DS_SEL

◆ KERNEL_TSS

◆ KERNEL_TSS_SEL

◆ ltr

◆ MEMALIGN

◆ MPINFOADDR

◆ MULTIBOOT_BOOTLOADER_MAGIC

◆ MULTIBOOT_HEADER_FLAGS

◆ MULTIBOOT_HEADER_MAGIC

◆ MULTIBOOT_HEADER_SIZE

◆ PAGEDIR_MAX

◆ PAGEMASK

◆ PAGESHIFT

◆ PAGESIZE

◆ PAGETAB_MAX

◆ SECTIONMASK

◆ tlb_flush

◆ tlb_flush_all

◆ USER_CS

◆ USER_CS_SEL

◆ USER_DS

◆ USER_DS_SEL

Typedef Documentation

◆ AoutSymbolTable

◆ CPURegs

◆ CPUState

◆ ElfSectionHeaderTable

◆ IRQRegs0

◆ IRQRegs3

◆ MultibootInfo

◆ MultibootMemoryMap

◆ MultibootModule

◆ Segment

◆ SegRegs

◆ TSS

Function Documentation